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lt1940/lt1940l 1 1940fa typical applicatio u features applicatio s u descriptio u n disk drives n dsp power supplies n wall transformer regulation n distributed power regulation n dsl modems n cable modems n wide input voltage range lt1940: 3.6v to 25v lt1940l: 3.6v to 7v n two 1.4a output switching regulators with internal power switches n constant 1.1mhz switching frequency n anti-phase switching reduces ripple n independent shutdown/soft-start pins n independent power good indicators ease supply sequencing n uses small inductors and ceramic capacitors n small 16-lead thermally enhanced tssop surface mount package dual monolithic 1.4a, 1.1mhz step-down switching regulator the lt ? 1940 is a dual current mode pwm step-down dc/dc converter with internal 2a power switches. both con- verters are synchronized to a single 1.1mhz oscillator and run with opposite phases, reducing input ripple current. the output voltages are set with external resistor dividers, and each regulator has independent shutdown and soft-start circuits. each regulator generates a power-good signal when its output is in regulation, easing power supply se- quencing and interfacing with microcontrollers and dsps. the lt1940s 1.1mhz switching frequency allows the use of tiny inductors and capacitors, resulting in a very small dual 1.4a output solution. constant frequency and ceramic capacitors combine to produce low, predictable output ripple voltage. with its wide input range of 3.6v to 25v, the lt1940 regulates a wide variety of power sources, from 4-cell batteries and 5v logic rails to unregulated wall trans- formers, lead acid batteries and distributed-power supplies. the lt1940l is intended to operate from regulated 5v supplies. a current mode pwm architecture provides fast transient response with simple compensation components and cycle-by-cycle current limiting. frequency foldback and thermal shutdown provide additional protection. , ltc and lt are registered trademarks of linear technology corporation. figure 1. 3.3v and 5v dual output step-down converter with output sequencing (lt1940) efficiency vs load current v in 7v to 25v boost1 sw1 fb1 v c1 run/ss1 run/ss2 boost2 sw2 fb2 v c2 pg1 pg2 lt1940 v in gnd 1940 f01 330pf 10 f 10 f 4.7 f 0.1 f 0.1 f 15k 330pf 15k 10.0k 16.5k 100k 30.1k 10.0k 4.7 h 3.3 h power good out2 5v 1.4a out1 3.3v 1.4a ups140 ups140 cmdsh-3 1nf cmdsh-3 load current (a) 0 efficiency (%) 100 90 80 70 60 0.5 1.0 1940 f01b 1.5 v in = 12v v out = 5v v out = 3.3v
lt1940/lt1940l 2 1940fa v in voltage lt1940 .................................................... (C0.3), 25v lt1940l ................................................... (C0.3), 7v boost pin voltage lt1940 ................................................................ 35v lt1940l ............................................................. 16v boost pin above sw pin lt1940 ................................................................ 25v lt1940l ............................................................. 16v pg pin voltage lt1940 ................................................................ 25v lt1940l ............................................................... 7v sw voltage ................................................................v in run/ss, fb pins ...................................................... 6v maximum junction temperature .......................... 125 c operating temperature range (note 2) ...C40 c to 85 c storage temperature range ..................C65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number t jmax = 125 c, q ja = 45 c/w, q jc = 10 c/w lt1940efe LT1940LEFE absolute axi u rati gs w ww u package/order i for atio uu w (note 1) electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 5v, v boost = 8v unless otherwise noted. (note 2) parameter conditions min typ max units minimum operating voltage l 3.4 3.6 v quiescent current not switching 3.8 4.8 ma shutdown current v runss = 0v 30 45 m a feedback voltage 1.230 1.250 1.270 v 0 c to 70 c l 1.225 1.250 1.270 v C40 c to 85 c l 1.215 1.250 1.270 v fb pin bias current v fb = 1.25v, v c = 0.4v l 240 1200 na reference line regulation lt1940: v in 5v to 25v 0.005 %/v lt1940l: v in 4v to 7v 0.005 %/v error amp gm 330 umhos error amp voltage gain 180 v c source current v fb = 1v 42 m a v c sink current v fb = 1.5v 60 m a v c pin to switch current gain 2.4 a/v v c switching threshold 0.75 v v c clamp voltage 1.8 v switching frequency v fb = 1.1v 1 1.1 1.25 mhz l 0.95 1.1 1.35 mhz switching phase 150 180 210 deg maximum duty cycle l 78 88 % frequency shift threshold on fb f sw = 1mhz 0.5 v consult ltc marketing for parts specified with wider operating temperature ranges. fe package 16-lead plastic tssop exposed pad (pin 17) is gnd must be soldered to pcb 1 2 3 4 5 6 7 8 top view 16 15 14 13 12 11 10 9 boost1 sw1 v in v in v in v in sw2 boost2 fb1 v c1 pg1 run/ss1 run/ss2 pg2 v c2 fb2 17 fe part marking 1940efe 1940lefe
lt1940/lt1940l 3 1940fa note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: the lt1940e is guaranteed to meet performance specifications from 0 c to 70 c. specifications over the C40 c to 85 c operating temperature range are assured by design, characterization and correlation with statistical process controls. electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 5v, v boost = 8v unless otherwise noted. (note 2) parameter conditions min typ max units foldback frequency v fb = 0v 150 khz switch current limit note 3 1.8 2.4 3.2 a switch v cesat i sw = 1a 210 320 mv switch leakage current 10 m a minimum boost voltage above switch (note 4) i sw = 1a 1.8 2.5 v boost pin current i sw = 1a 20 30 ma run/ss current 2.3 m a run/ss threshold 0.3 0.6 v pg threshold offset v fb rising 90 125 160 mv pg voltage output low v fb = 1v, i pg = 250 m a 0.22 0.4 v pg pin leakage v pg = 2v 0.1 1 m a note 3: current limit is guaranteed by design and/or correlation to static test. slope compensation reduces current limit at high duty cycle. note 4: this is the minimum voltage across the boost capacitor needed to guarantee full saturation of the internal power switch. typical perfor a ce characteristics uw efficiency, v out = 3.3v efficiency, v out = 5v load current (a) 0 efficiency (%) 90 80 70 60 50 0.5 1.0 1940 g01 1.5 v out = 1.8v l = 2.2 h (sumida cr43-2r2) t a = 25 c v in = 5v load current (a) 0 efficiency (%) 100 90 80 70 60 50 0.5 1.0 1940 g02 1.5 v out = 3.3v l = 3.3 h (sumida cr43-3r3) t a = 25 c v in = 5v v in = 18v v in = 12v load current (a) 0 efficiency (%) 100 90 80 70 60 0.5 1.0 1940 g03 1.5 v out = 5v l = 4.7 h (sumida cr43-4r7) t a = 25 c v in = 8v v in = 18v v in = 12v efficiency, v out = 1.8v
lt1940/lt1940l 4 1940fa current limit vs duty cycle v out vs temperature frequency foldback i run/ss vs temperature typical perfor a ce characteristics uw duty cycle (%) 0 current limit (a) typical 80 1940 g08 20 40 60 100 3.0 2.5 2.0 1.5 1.0 0.5 0 minimum ?0 ?5 0 25 50 75 100 125 temperature ( c) v out (v) 1940 g09 3.40 3.35 3.30 3.25 3.20 channel 1, figure 1, v in = 12v switch current (a) 0 boost current (ma) 20 30 2.0 1940 g07 10 0 0.5 1.0 1.5 40 frequency vs temperature boost pin current temperature ( c) ?0 frequency (mhz) 1.3 1.2 1.1 1.0 0.9 ?5 0 25 50 1940 g10 75 100 125 feedback voltage (v) switching frequency (mhz) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 1940 g11 0 0.2 0.4 0.6 0.8 1.0 1.2 temperature ( c) ?0 0 run/ss current ( a) 0.5 1.0 1.5 2.0 3.0 ?5 02550 1940 g12 75 100 125 2.5 maximum load current, v out = 1.8v switch v cesat maximum load current, v out = 3.3v sw current (a) 0 switch voltage (mv) 200 300 2.0 1940 g06 100 0 0.5 1.0 1.5 400 t a = 25 c input voltage (v)* 0 load current (a) 1.4 1.6 12 14 1940 g04 1.2 1.0 8 4 2 6 10 16 1.8 l = 2.2 h l = 1.5 h l = 1 h input voltage (v)* 0 load current (a) 1.4 1.6 20 1940 g05 1.2 1.0 5 10 15 25 1.8 l = 4.7 h l = 3.3 h l = 2.2 h slope compensation requires l > 2.2 h for v in < 7 with v out = 3.3v *maximum v in is 7v for lt1940l.
lt1940/lt1940l 5 1940fa uu u pi fu ctio s boost1, boost2 (pins 1, 8): the boost pins are used to provide drive voltages, higher than the input voltage, to the internal bipolar npn power switches.tie through a diode from v out or from v in . sw1, sw2 (pins 2, 7): the sw pins are the outputs of the internal power switches. connect these pins to the induc- tors, catch diodes and boost capacitors. v in (pins 3, 4, 5, 6): the v in pins supply current to the lt1940s internal regulator and to the internal power switches. these pins must be tied to the same source, and must be locally bypassed. fb1, fb2 (pins 9, 16): the lt1940 regulates each feed- back pin to 1.25v. connect the feedback resistor divider taps to these pins. v c1 , v c2 (pins 10, 15): the v c pins are the outputs of the internal error amps. the voltages on these pins control the peak switch currents. these pins are normally used to compensate the control loops, but can also be used to override the loops. pull these pins to ground with an open drain to shut down each switching regulator. pg1, pg2 (pins 11, 14): the power good pins are the open collector outputs of an internal comparator. pg remains low until the fb pin is within 10% of the final regulation voltage. as well as indicating output regulation, the pg pins can be used to sequence the two switching regulators. these pins can be left unconnected. the pg outputs are valid when v in is greater than 2.4v and either of the run/ss pins is high. the pg comparators are disabled in shutdown. run/ss1, run/ss2 (pins 12, 13): the run/ss pins are use to shut down the individual switching regulators and the internal bias circuits. they also provide a soft-start function. to shut down either regulator, pull the run/ss pin to ground with an open drain or collector. tie a capacitor from these pins to ground to limit switch current during start-up. if neither feature is used, leave these pins unconnected. gnd (pin 17): the exposed pad of the package provides both electrical contact to ground and good thermal con- tact to the printed circuit board. the exposed pad must be soldered to the circuit board for proper operation. run/ss thresholds vs temperature 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 runn/ss thresholds (v) temperature ( c) ?0 25 75 1940 g13 ?5 0 50 100 125 to switch to run load current (ma) 1 minimum input voltage (v) 6.0 5.5 5.0 4.5 4.0 3.5 3.0 10 100 1000 1940 g14 v in to start boost diode tied to output boost diode tied to input v in to run t a = 25 c d boost = bat54 load current (ma) 1 minimum input voltage (v) 7.5 7.0 6.5 6.0 5.5 5.0 4.5 10 100 1000 1940 g14 v in to start boost diode tied to output v in to run t a = 25 c d boost = bat54 boost diode tied to input minimum input voltage, v out = 3.3v minimum input voltage, v out = 5v typical perfor a ce characteristics uw
lt1940/lt1940l 6 1940fa the lt1940 is a dual, constant frequency, current mode buck regulator with internal 2a power switches. the two regulators share common circuitry including input source, voltage reference and oscillator, but are otherwise inde- pendent. this section describes the operation of the lt1940; refer to the block diagram. if the run/ss (run/soft-start) pins are both tied to ground, the lt1940 is shut down and draws 30 m a from the input source tied to v in . internal 2 m a current sources charge external soft-start capacitors, generating voltage ramps at block diagra w + + + + r sq slave osc int reg and ref master osc run/ss2 run/ss1 2 a 2 a clk1 clk2 v in 1.25v 125mv i limit clamp run/ss pg c c c f r c gnd error amp slope v c 0.75v 0.5v clk r1 c1 c in sw fb boost v in in d2 c3 l1 d1 c1 r2 out 1940 f02 these pins. if either run/ss pin exceeds 0.6v, the internal bias circuits turn on, including the internal regulator, 1.25v reference and 1.1mhz master oscillator. in this state, the lt1940 draws 3.5ma from v in , whether one or both run/ss pins are high. neither switching regulator will begin to operate until its run/ss pin reaches ~0.8v. the master oscillator generates two clock signals of opposite phase. the two switchers are current mode step-down regula- tors. this means that instead of directly modulating the figure 2. block diagram of the lt1940 with associated external components (one of two switching regulators shown)
lt1940/lt1940l 7 1940fa block diagra w each switcher contains an independent oscillator. this slave oscillator is normally synchronized to the master oscillator. however, during start-up, short-circuit or over- load conditions, the fb pin voltage will be near zero and an internal comparator gates the master oscillator clock signal. this allows the slave oscillator to run the regulator at a lower frequency. this frequency foldback behavior helps to limit switch current and power dissipation under fault conditions. the switch driver operates from either the input or from the boost pin. an external capacitor and diode are used to generate a voltage at the boost pin that is higher than the input supply. this allows the driver to fully saturate the internal bipolar npn power switch for efficient operation. a power good comparator trips when the fb pin is at 90% of its regulated value. the pg output is an open collector transistor that is off when the output is in regulation, allowing an external resistor to pull the pg pin high. power good is valid when the lt1940 is enabled (either run/ss pin is high) and v in is greater than ~2.4v. duty cycle of the power switch, the feedback loop controls the peak current in the switch during each cycle. this current mode control improves loop dynamics and pro- vides cycle-by-cycle current limit. the block diagram shows only one of the two switching regulators. a pulse from the slave oscillator sets the rs flip-flop and turns on the internal npn bipolar power switch. current in the switch and the external inductor begins to increase. when this current exceeds a level determined by the voltage at v c , current comparator c1 resets the flip-flop, turning off the switch. the current in the inductor flows through the external schottky diode, and begins to decrease. the cycle begins again at the next pulse from the oscillator. in this way the voltage on the v c pin controls the current through the inductor to the output. the internal error amplifier regulates the output voltage by continually adjusting the v c pin voltage. the threshold for switching on the v c pin is 0.75v, and an active clamp of 1.8v limits the output current. the v c pin is also clamped to the run/ss pin voltage. as the internal current source charges the external soft-start capacitor, the current limit increases slowly. applicatio s i for atio wu u u fb resistor network the output voltage is programmed with a resistor divider between the output and the fb pin. choose the 1% resistors according to: r1 = r2(v out /1.25 C 1) r2 should be 10.0k w or less to avoid bias current errors. reference designators refer to the block diagram in figure 2. input voltage range the minimum input voltage is determined by either the lt1940s minimum operating voltage of ~3.5v, or by its maximum duty cycle. the duty cycle is the fraction of time that the internal switch is on and is determined by the input and output voltages: dc = (v out + v d )/(v in C v sw + v d ) where v d is the forward voltage drop of the catch diode (~0.4v) and v sw is the voltage drop of the internal switch (~0.3v at maximum load). this leads to a minimum input voltage of: v inmin = (v out + v d )/dc max - v d + v sw with dc max = 0.78. a more detailed analysis includes inductor loss and the dependence of the diode and switch drop on operating current. a common application where the maximum duty cycle limits the input voltage range is the conversion of 5v to 3.3v. the maximum load current that the lt1940 can deliver at 3.3v depends on the accuracy of the 5v input supply. with a low loss inductor (dcr less than 80m w ), the lt1940 can deliver 1a for v in > 4.7v and 1.4a for v in > 4.85v.
lt1940/lt1940l 8 1940fa applicatio s i for atio wu u u (v out /v in < 0.5), there is a minimum inductance required to avoid subharmonic oscillations. see an19. the discus- sion below assumes continuous inductor current. the current in the inductor is a triangle wave with an average value equal to the load current. the peak switch current is equal to the output current plus half the peak-to- peak inductor ripple current. the lt1940 limits its switch current in order to protect itself and the system from overload faults. therefore, the maximum output current that the lt1940 will deliver depends on the current limit, the inductor value, and the input and output voltages. l is chosen based on output current requirements, output voltage ripple requirements, size restrictions and effi- ciency goals. when the switch is off, the inductor sees the output voltage plus the catch diode drop. this gives the peak-to- peak ripple current in the inductor: d i l = (1 C dc)(v out + v d )/(l ? f) where f is the switching frequency of the lt1940 and l is the value of the inductor. the peak inductor and switch current is i swpk = i lpk = i out + d i l /2. to maintain output regulation, this peak current must be less than the lt1940s switch current limit i lim . i lim is at least 1.8a at low duty cycle and decreases linearly to 1.5a at dc = 0.8. the maximum output current is a function of the chosen inductor value: i outmax = i lim C d i l /2 = 1.8a ? (1 C 0.21 ? dc) C d i l /2 if the inductor value is chosen so that the ripple current is small, then the available output current will be near the switch current limit. one approach to choosing the inductor is to start with the simple rule given above, look at the available inductors, and choose one to meet cost or space goals. then use these equations to check that the lt1940 will be able to deliver the required output current. note again that these equations assume that the inductor current is continuous. discontinuous operation occurs when i out is less than d i l /2 as calculated above. the maximum input voltage is determined by the absolute maximum ratings of the v in and boost pins and by the minimum duty cycle dc min = 0.15: v inmax = (v out + v d )/dc min C v d + v sw . this limits the maximum input voltage to ~14v with v out = 1.8v and ~19v with v out = 2.5v. note that this is a restriction on the operating input voltage; the circuit will tolerate transient inputs up to the absolute maximum rating. for the lt1940l, the maximum input voltage is 7v. inductor selection and maximum output current a good first choice for the inductor value is: l = (v out + v d )/1.2 where v d is the voltage drop of the catch diode (~0.4v) and l is in m h. with this value the maximum load current will be ~1.4a, independent of input voltage. the inductors rms current rating must be greater than your maximum load current and its saturation current should be about 30% higher. to keep efficiency high, the series resistance (dcr) should be less than 0.1 w . table 1 lists several vendors and types that are suitable. of course, such a simple design guide will not always result in the optimum inductor for your application. a larger value provides a slightly higher maximum load current, and will reduce the output voltage ripple. if your load is lower than 1.4a, then you can decrease the value of the inductor and operate with higher ripple current. this allows you to use a physically smaller inductor, or one with a lower dcr resulting in higher efficiency. be aware that if the inductance differs from the simple rule above, then the maximum load current will depend on input voltage. there are several graphs in the typical performance character- istics section of this data sheet that show the maximum load current as a function of input voltage and inductor value for several popular output voltages. also, low inductance may result in discontinuous mode operation, which is okay, but further reduces maximum load current. for details of maximum output current and discontinuous mode operation, see linear technology application note 44. finally, for duty cycles greater than 50%
lt1940/lt1940l 9 1940fa input capacitor selection bypass the input of the lt1940 circuit with a 4.7 m f or higher ceramic capacitor of x7r or x5r type. a lower value or a less expensive y5v type can be used if there is additional bypassing provided by bulk electrolytic or tantalum capacitors. the following paragraphs describe the input capacitor considerations in more detail. step-down regulators draw current from the input supply in pulses with very fast rise and fall times. the input capacitor is required to reduce the resulting voltage ripple at the lt1940 and to force this very high frequency switching current into a tight local loop, minimizing emi. the input capacitor must have low impedance at the switching frequency to do this effectively, and it must have an adequate ripple current rating. with two switchers operating at the same frequency but with different phases and duty cycles, calculating the input capacitor rms current is not simple. however, a conservative value is the rms input current for the channel that is delivering most power (v out ? i out ). this is given by: c inrms = i out ? [v out ? (v in C v out )]/v in < i out /2 and is largest when v in = 2v out (50% duty cycle). as the second, lower power channel draws input current, the input capacitors rms current actually decreases as the out-of-phase current cancels the current drawn by the higher power channel. considering that the maximum load current from a single channel is ~1.4a, rms ripple current will always be less than 0.7a. the high frequency of the lt1940 reduces the energy storage requirements of the input capacitor, so that the capacitance required is less than 10 m f. the combination of small size and low impedance (low equivalent series resistance or esr) of ceramic capacitors make them the preferred choice. the low esr results in very low voltage ripple and the capacitors can handle plenty of ripple current. they are also comparatively robust and can be used in this application at their rated voltage. x5r and x7r types are stable over temperature and applied voltage, and give dependable service. other types (y5v and z5u) have very large temperature and voltage coefficients of capaci- tance, so they may have only a small fraction of their nominal capacitance in your application. while they will still handle the rms ripple current, the input voltage ripple may become fairly large, and the ripple current may end up flowing from your input supply or from other bypass capacitors in your system, as opposed to being fully sourced from the local input capacitor. an alternative to a high value ceramic capacitor is a lower value along with a larger electrolytic capacitor, for ex- ample a 1 m f ceramic capacitor in parallel with a low esr tantalum capacitor. for the electrolytic capacitor, a value larger than 10 m f will be required to meet the esr and ripple current requirements. because the input capacitor applicatio s i for atio wu u u table 1. inductors. part number value i sat dcr height ( m h) (a) dc ( w ) (mm) sumida cr43-1r4 1.4 2.52 0.056 3.5 cr43-2r2 2.2 1.75 0.071 3.5 cr43-3r3 3.3 1.44 0.086 3.5 cr43-4r7 4.7 1.15 0.109 3.5 cdrh3d16-1r5 1.5 1.55 0.040 1.8 cdrh3d16-2r2 2.2 1.20 0.050 1.8 cdrh3d16-3r3 3.3 1.10 0.063 1.8 cdrh4d28-3r3 3.3 1.57 0.049 3.0 cdrh4d28-4r7 4.7 1.32 0.072 3.0 cdrh5d28-5r3 5.3 1.9 0.028 3.0 cdrh5d18-4r1 4.1 1.95 0.042 2.0 coilcraft do1606t-152 1.5 2.10 0.060 2.0 do1606t-222 2.2 1.70 0.070 2.0 do1606t-332 3.3 1.30 0.100 2.0 do1606t-472 4.7 1.10 0.120 2.0 do1608c-152 1.5 2.60 0.050 2.9 do1608c-222 2.2 2.30 0.070 2.9 do1608c-332 3.3 2.00 0.080 2.9 do1608c-472 4.7 1.50 0.090 2.9 1812ps-222m 2.2 1.7 0.070 3.81 1008ps-182m 1.8 2.1 0.090 2.74 murata lqh32cn1r0m11l 1.0 1.00 0.078 2.2 lqh32cn2r2m11l 2.2 0.79 0.126 2.2 lqh43cn1r5m01l 1.5 1.00 0.090 2.8 lqh43cn2r2m01l 2.2 0.90 0.110 2.8 lqh43cn3r3m01l 3.3 0.80 0.130 2.8
lt1940/lt1940l 10 1940fa is likely to see high surge currents when the input source is applied, tantalum capacitors should be surge rated. the manufacturer may also recommend operation below the rated voltage of the capacitor. be sure to place the 1 m f ceramic as close as possible to the v in and gnd pins on the ic for optimal noise immunity. a final caution is in order regarding the use of ceramic capacitors at the input. a ceramic input capacitor can combine with stray inductance to form a resonant tank circuit. if power is applied quickly (for example by plug- ging the circuit into a live power source) this tank can ring, doubling the input voltage and damaging the lt1940. the solution is to either clamp the input voltage or dampen the tank circuit by adding a lossy capacitor in parallel with the ceramic capacitor. for details, see an88. output capacitor selection for 5v and 3.3v outputs with greater than 1a output, a 10 m f 6.3v ceramic capacitor (x5r or x7r) at the output results in very low output voltage ripple and good transient response. for lower voltages, 10 m f is adequate but in- creasing c out to 15 m f or 22 m f will improve transient performance. other types and values can be used; the following discusses tradeoffs in output ripple and tran- sient performance. the output capacitor filters the inductor current to gener- ate an output with low voltage ripple. it also stores energy in order satisfy transient loads and to stabilize the lt1940s control loop. because the lt1940 operates at a high frequency, you dont need much output capacitance. also, the current mode control loop doesnt require the pres- ence of output capacitor series resistance (esr). for these reasons, you are free to use ceramic capacitors to achieve very low output ripple and small circuit size. estimate output ripple with the following equations: v ripple = d i l /(8f c out ) for ceramic capacitors, and v ripple = d i l esr for electrolytic capacitors (tantalum and aluminum); where d i l is the peak-to-peak ripple current in the induc- tor. the rms content of this ripple is very low, and the rms current rating of the output capacitor is usually not of concern. another constraint on the output capacitor is that it must have greater energy storage than the inductor; if the stored energy in the inductor is transferred to the output, you would like the resulting voltage step to be small compared to the regulation voltage. for a 5% overshoot, this require- ment becomes c out > 10l(i lim /v out )^2. finally, there must be enough capacitance for good tran- sient performance. the last equation gives a good starting point. alternatively, you can start with one of the designs in this data sheet and experiment to get the desired performance. this topic is covered more thoroughly in the section on loop compensation. the high performance (low esr), small size and robust- ness of ceramic capacitors make them the preferred type for lt1940 applications. however, all ceramic capacitors are not the same. as mentioned above, many of the higher value capacitors use poor dielectrics with high tempera- ture and voltage coefficients. in particular, y5v and z5u types lose a large fraction of their capacitance with applied voltage and temperature extremes. because the loop stability and transient response depend on the value of c out, you may not be able to tolerate this loss. use x7r and x5r types. you can also use electrolytic capacitors. the esrs of most aluminum electrolytics are too large to deliver low output ripple. tantalum and newer, lower esr organic electro- lytic capacitors intended for power supply use are suit- able, and the manufacturers will specify the esr. the choice of capacitor value will be based on the esr required for low ripple. because the volume of the capacitor deter- mines its esr, both the size and the value will be larger than a ceramic capacitor that would give you similar ripple performance. one benefit is that the larger capacitance may give better transient response for large changes in load current. table 2 lists several capacitor vendors. applicatio s i for atio wu u u
lt1940/lt1940l 11 1940fa table 2. low-esr surface mount capacitors vendor type series taiyo yuden ceramic x5r, x7r avx ceramic x5r, x7r tantalum tps kemet tantalum t491,t494,t495 ta organic t520 al organic a700 sanyo ta or al organic poscap panasonic al organic sp cap tdk ceramic x5r, x7r catch diode use a 1a schottky diode for the catch diode (d1 in figure 2). the diode must have a reverse voltage rating greater than the maximum input voltage. the on semi- conductor mbrm120lt3 (20v) and mbrm130lt3 (30v) are good choices; they have a tiny package with good thermal properties. many vendors have surface mount versions of the 1n5817 (20v) and 1n5818 (30v) 1a schottky diodes such as the microsemi ups120 that are suitable. boost pin considerations the capacitor and diode tied to the boost pin generate a voltage that is higher than the input voltage. in most cases a 0.1 m f capacitor and fast switching diode (such as the cmdsh-3 or fmmd914) will work well. figure 3 shows three ways to arrange the boost circuit. the boost pin must be more than 2.5v above the sw pin for full effi- ciency. for outputs of 3.3v and higher the standard circuit (figure 3a) is best. for outputs between 2.8v and 3.3v, use a small schottky diode (such as the bat-54). for lower output voltages the boost diode can be tied to the input (figure 3b). the circuit in figure 3a is more efficient because the boost pin current comes from a lower voltage source. finally, as shown in figure 3c, the anode of the boost diode can be tied to another source that is at least 3v. for example, if you are generating 3.3v and 1.8v and the 3.3v is on whenever the 1.8v is on, the 1.8v boost diode can be connected to the 3.3v output. in any case, you must also be sure that the maximum voltage at the boost pin is less than the maximum specified in the absolute maximum ratings section. figure 3. generating the boost voltage v in boost gnd sw v in lt1940 (3a) d2 v out c3 v boost ?v sw @ v out max v boost @ v in + v out v in boost gnd sw v in lt1940 (3b) d2 v out c3 v boost ?v sw @ v in max v boost @ 2v in v in boost gnd sw v in lt1940 (3d) 1940 f03 v out max v boost ?v sw @ v in2 max v boost @ v in2 minimum value for v in2 = v in + 3v v in2 >v in + 3v d2 v in boost gnd sw v in lt1940 (3c) 1940 f03 v out v boost ?v sw @ v in2 max v boost @ v in2 + v in minimum value for v in2 = 3v d2 v in2 > 3v c3 applicatio s i for atio wu u u
lt1940/lt1940l 12 1940fa the boost circuit can also run directly from a dc voltage that is higher than the input voltage by more than 3v, as in figure 3d. the diode is used to prevent damage to the lt1940 in case v in2 is held low while v in is present. the circuit saves several components (both boost pins can be tied to d2). however, efficiency may be lower and dissipation in the lt1940 may be higher. also, if v in2 is absent, the lt1940 will still attempt to regulate the output, but will do so with very low efficiency and high dissipation because the switch will not be able to saturate, dropping 1.5v to 2v in conduction. the minimum input voltage of an lt1940 application is limited by the minimum operating voltage (< 3.6v) and by the maximum duty cycle as outlined above. for proper start-up, the minimum input voltage is also limited by the boost circuit. if the input voltage is ramped slowly, or the lt1940 is turned on with its run/ss pin when the output is already in regulation, then the boost capacitor may not be fully charged. because the boost capacitor is charged with the energy stored in the inductor, the circuit will rely on some minimum load current to get the boost circuit running properly. this minimum load will depend on input and output voltages, and on the arrangement of the boost circuit. the minimum load generally goes to zero once the circuit has started. the typical performance characteris- tics section shows plots of the minimum load current to start and to run as a function of input voltage for 3.3v and 5v outputs. in many cases the discharged output capaci- tor will present a load to the switcher which will allow it to start. the plots show the worst-case situation where v in is ramping very slowly. use a schottky diode (such as the bat-54) for the lowest start-up voltage. frequency compensation the lt1940 uses current mode control to regulate the output. this simplifies loop compensation. in particular, the lt1940 does not require the esr of the output capacitor for stability so you are free to use ceramic capacitors to achieve low output ripple and small circuit size. frequency compensation is provided by the components tied to the v c pin. generally a capacitor and a resistor in series to ground determine loop gain. in addition, there is a lower value capacitor in parallel. this capacitor is not part of the loop compensation but is used to filter noise at the switching frequency. loop compensation determines the stability and transient performance. designing the compensation network is a bit complicated and the best values depend on the appli- cation and in particular the type of output capacitor. a practical approach is to start with one of the circuits in this data sheet that is similar to your application and tune the compensation network to optimize the performance. sta- bility should then be checked across all operating condi- tions, including load current, input voltage and tempera- ture. the lt1375 data sheet contains a more thorough discussion of loop compensation and describes how to test the stability using a transient load. figure 4 shows an equivalent circuit for the lt1940 control loop. the error amp is a transconductance ampli- fier with finite output impedance. the power section, consisting of the modulator, power switch and inductor, is modeled as a transconductance amplifier generating an output current proportional to the voltage at the v c pin. note that the output capacitor integrates this current, and that the capacitor on the v c pin (c c ) integrates the error amplifier output current, resulting in two poles in the loop. in most cases a zero is required and comes from either the output capacitor esr or from a resistor in series with c c . this simple model works well as long as the value of the inductor is not too high and the loop crossover frequency is much lower than the switching frequency. a phase lead capacitor (c pl ) across the feedback divider may improve the transient response. figure 4. model for loop response applicatio s i for atio wu u u + 1.25v v sw v c lt1940 gnd 1940 f05 r1 output esr c f c c r c 500k error amplifier fb r2 c1 c1 current mode power stage g m = 2.5mho g m = 340 mho + polymer or tantalum ceramic c pl
lt1940/lt1940l 13 1940fa soft-start and shutdown the run/ss (run/soft-start) pins are used to place the individual switching regulators and the internal bias cir- cuits in shutdown mode. they also provide a soft-start function. to shut down either regulator, pull the run/ss pin to ground with an open-drain or collector. if both run/ss pins are pulled to ground, the lt1940 enters its shutdown mode with both regulators off and quiescent current reduced to ~30 m a. internal 2 m a current sources pull up on each pin. if either pin reaches ~0.5v, the internal bias circuits start and the quiescent current increases to ~3.5ma. if a capacitor is tied from the run/ss pin to ground, then the internal pull-up current will generate a voltage ramp on this pin. this voltage clamps the v c pin, limiting the peak switch current and therefore input current during start up. a good value for the soft-start capacitor is c out /10,000, where c out is the value of the output capacitor. the run/ss pins can be left floating if the shutdown feature is not used. they can also be tied together with a single capacitor providing soft-start. the internal current sources will charge these pins to ~2.5v. the run/ss pins provide a soft-start function that limits peak input current to the circuit during start-up. this helps to avoid drawing more current than the input source can supply or glitching the input supply when the lt1940 is enabled. the run/ss pins do not provide an accurate delay to start or an accurately controlled ramp at the output voltage, both of which depend on the output capacitance and the load current. however, the power good indicators can be used to sequence the two outputs, as described below. power good indicators the pg pin is the open collector output of an internal comparator. pg remains low until the fb pin is within 10% of the final regulation voltage. tie the pg pin to any supply with a pull-up resistor that will supply less than 250 m a. note that this pin will be open when the lt1940 is placed in shutdown mode (both run/ss pins at ground) regard- less of the voltage at the fb pin. power good is valid when the lt1940 is enabled (either run/ss pin is high) and v in is greater than ~2.4v. output sequencing the pg and run/ss pins can be used to sequence the two outputs. figure 5 shows several circuits to do this. in each case channel 1 starts first. note that these circuits se- quence the outputs during start-up. when shut down the two channels turn off simultaneously. in figure 5a, a larger capacitor on run/ss2 delays chan- nel 2 with respect to channel 1. the soft-start capacitor on run/ss2 should be at least twice the value of the capacitor on run/ss1. a larger ratio may be required, depending on the output capacitance and load on each channel. make sure to test the circuit in the system before deciding on final values for these capacitors. the circuit in figure 5b requires the fewest components, with both channels sharing a single soft-start capacitor. the power good comparator of channel 1 disables channel 2 until output 1 is in regulation. for independent control of channel 2, use the circuit in figure 5c. the capacitor on run/ss1 is smaller than the capacitor on run/ss2. this allows the lt1940 to start up and enable its power good comparator before run/ss2 gets high enough to allow channel 2 to start switching. channel 2 only operates when it is enabled with the external control signals and output 1 is in regulation. the circuit in figure 5a leaves both power good indicates free. however, the circuits in figures 5b and 5c have another advantage. as well as sequencing the two outputs at start-up, they also disable channel 2 if output 1 falls out of regulation (due to a short circuit or a collapsing input voltage). finally, be aware that the circuit in figure 5d does not work , because the power good comparators are disabled in shutdown. when the system is placed in shutdown mode by pulling down on run/ss1, then output 1 will go low, pg1 will pull down on run/ss2, and the lt1940 will enter its low current shutdown state. this disables pg1, and run/ss2 ramps up again to enable the lt1940. the circuit will oscillate and pull extra current from the input. applicatio s i for atio wu u u
lt1940/lt1940l 14 1940fa shorted input protection if the inductor is chosen so that it wont saturate exces- sively, the lt1940 will tolerate a shorted output. there is another situation to consider in systems where the output will be held high when the input to the lt1940 is absent. if the v in and one of the run/ss pins are allowed to float, then the lt1940s internal circuitry will pull its quiescent current through its sw pin. this is fine if your system can tolerate a few ma of load in this state. with both run/ss pins grounded, the lt1940 enters shutdown mode and the sw pin current drops to ~30 m a. however, if the v in pin is grounded while the output is held high, then parasitic diodes inside the lt1940 can pull large currents from the output through the sw pin and the v in pin. a schottky diode in series with the input to the lt1940 will protect the lt1940 and the system from a shorted or reversed input. applicatio s i for atio wu u u figure 5. several methods of sequencing the two outputs. channel 1 starts first. figure 6. diode d4 prevents a shorted input from discharging a backup battery tied to the output. pcb layout for proper operation and minimum emi, care must be taken during printed circuit board (pcb) layout. figure 7 shows the high-di/dt paths in the buck regulator circuit. note that large, switched currents flow in the power switch, the catch diode and the input capacitor. the loop formed by these components should be as small as possible. these components, along with the inductor and output capacitor, should be placed on the same side of the circuit board, and their connections should be made on that layer. place a local, unbroken ground plane below these components, and tie this ground plane to system ground at one location, ideally at the ground terminal of the output capacitor c2. additionally, the sw and boost nodes should be kept as small as possible. figure 8 shows recommended component placement with trace and via locations. off 1940 f05 run/ss1 pg1 on gnd off run/ss1 on gnd run/ss2 off run/ss1 on off2 on2 gnd run/ss2 run/ss2 v c2 pg1 1nf 1nf 1nf 2.2nf 1nf 1.5nf 1.5nf (5b) fewest components (5c) independent control of channel 2 off run/ss1 on gnd run/ss2 pg1 (5d) doesn't work ! (5a) channel 2 is delayed v in v in v out sw lt1940 d4 parasitic diode 1940 f06
lt1940/lt1940l 15 1940fa thermal considerations the pcb must also provide heat sinking to keep the lt1940 cool. the exposed metal on the bottom of the package must be soldered to a ground plane. this ground should be tied to other copper layers below with thermal vias; these layers will spread the heat dissipated by the lt1940. place additional vias near the catch diodes. adding more copper to the top and bottom layers and tying this copper to the internal planes with vias can reduce thermal resistance further. with these steps, the thermal resistance from die (or junction) to ambient can be re- duced to q ja = 45 c/w. the power dissipation in the other power components catch diodes, boost diodes and inductors, cause addi- tional copper heating and can further increase what the ic sees as ambient temperature. see the lt1767 data sheets thermal considerations section. single, low-ripple 2.8a output the lt1940 can generate a single, low-ripple 2.8a output if the outputs of the two switching regulators are tied together and share a single output capacitor. by tying the two fb pins together and the two v c pins together, the two channels will share the load current. there are several advantages to this two-phase buck regulator. ripple cur- rents at the input and output are reduced, reducing voltage ripple and allowing the use of smaller, less expensive figure 8. a good pcb layout ensures proper low emi operation applicatio s i for atio wu u u figure 7. subtracting the current when the switch is on (a) from the current when the switch is off (b) reveals the path of the high frequency switching current (c) keep this loop small. the voltage on the sw and boost nodes will also be switched; keep these nodes as small as possible. finally, make sure the circuit is shielded with a local ground plane. v in sw gnd (7a) v in v sw c1 d1 c2 1940 f07 l1 sw gnd (7c) v in sw gnd (7b) i c1 via to local ground plane via to v in 1940 f08 gnd v out1 v out2
lt1940/lt1940l 16 1940fa capacitors. although two inductors are required, each will be smaller than the inductor required for a single-phase regulator. this may be important when there are tight height restrictions on the circuit. the typical applications section shows circuits with maximum heights of 1.4mm, 1.8mm and 2.1mm. there is one special consideration regarding the two- phase circuit. when the difference between the input voltage and output voltage is less than 2.5v, then the boost circuits may prevent the two channels from properly sharing current. if, for example, channel 1 gets started first, it can supply the load current, while channel 2 never switches enough current to get its boost capacitor charged. in this case, channel 1 will supply the load until it reaches current limit, the output voltage drops, and channel 2 gets started. the solution is to generate a boost supply gener- ated from either sw pin that will service both boost pins. the low profile, single output 5v to 3.3v converter shown in the typical applications section shows how to do this. generating an output under 1.25v the lt1940 regulates its feedback pins to 1.25v. two resistors can be used to program an output that is higher than 1.25v. generating an output voltage that is less than the internal reference is generally more difficult, but the lt1940 can easily generate an output voltage less than 1.25v if the other output is greater than 1.25v. figure 9 shows how. v out1 , which must be greater than 1.25v, is used as a reference voltage for the feedback divider from v out2 to the fb2 pin (r3 and r4). calculate the resistor values with these equations: r2/r1 = v out1 /1.25v - 1 r4/r3 = (1.25v C v out2 )/(v out1 C 1.25v) r5 prevents the current through r3 and r4 from pulling v out2 high when there is no load current. r5 < (r3 + r4) v out2 /(v out1 C v out2 ). if v out1 is out of regulation (during start-up or if it is overloaded or shorted) then v out2 will regulate to a higher voltage than intended. to avoid this, the power good output from the channel 1 (pg1) is tied to the compensa- tion pin (v c2 ) of the channel 2. this disables channel 2 until v out1 is in regulation. accuracy is good, especially when r4/r3 is small. for example, for v out1 = 3.3v and v out2 = 1.2v, choose r1 = 10k, r2 = 16.5k, r3 = 10k, r4 = 243 w and r5 = 4.7k. other linear technology publications application notes an19, an35 and an44 contain more detailed descriptions and design information for buck regulators and other switching regulators. the lt1376 data sheet has a more extensive discussion of output ripple, loop compensation and stability testing. design note dn100 shows how to generate a dual (+ and C) output supply using a buck regulator. figure 9. this circuit can be used when v out1 is greater than 1.25v and v out2 is less than 1.25v. applicatio s i for atio wu u u sw1 sw2 gnd pg1 v c2 fb1 fb2 lt1940 v out2 v out1 r2 r4 r3 r1 r5 1940 f09
lt1940/lt1940l 17 1940fa 5v/3.3v with tantalum output capacitors v in 7v to 25v boost1 sw1 fb1 v c1 pg1 run/ss1 boost2 sw2 fb2 v c2 pg2 run/ss2 lt1940 v in gnd 1940 ta03 100pf c2 47 f 10v c1 100 f 6.3v c3 4.7 f 0.1 f 0.1 f 20k 220pf 10.0k 10.0k 16.5k 100k 30.1k 100k l2 4.7 h l1 3.3 h 5 good 3v3 good out2 5v 1.2a out1 3.3v 1.2a d2 10.0k d1 d3 1nf 1nf d4 + + d1, d2: microsemi ups140 or on semi mbrm140 d3, d4: central cmdsh-3 l1: sumida cdrh4d28-3r3 l2: sumida cdrh4d28-4r7 c1: avx tpsc107m010r0150 c2: avx tpsc476m010r0350 c3: taiyo yuden tmk325bj475ml typical applicatio s u v in 4.7v to 14v 1940 ta01 330pf c2 10 f c1 22 f c3 4.7 f 0.1 f 0.1 f 15k 220pf 20k 10.0k 10.0k 100k 16.5k l2 3.3 h l1 2.2 h power good out2 3.3v 1a (1.4a for v in > 5v) out1 1.8v 1.4a d2 22.6k d1 d3 1nf d1, d2: microsemi ups120 d3, d4: central cmdsh-3 l1: sumida cr43-2r2 l2: sumida cr43-3r3 d4 c1: taiyo yuden jmk316bj226ml c2: taiyo yuden jmk316bj106ml c3: taiyo yuden emk316bj475ml boost1 sw1 fb1 v c1 run/ss1 run/ss2 boost2 sw2 fb2 v c2 pg1 pg2 lt1940 v in gnd 3.3v and 1.8v outputs with sequencing start-up waveforms v in 2v/div v out1 2v/div v out2 2v/div power good 2v/div 50 s/div 1940 ta01b
lt1940/lt1940l 18 1940fa 3.3v, 5v low ripple, low profile 12v to 3.3v/2.4a maximum height = 2.1mm v in 10v to 25v boost1 sw1 fb1 v c1 pg1 run/ss1 boost2 sw2 fb2 v c2 pg2 run/ss2 lt1940 v in gnd 1940 ta05 220pf c2 10 f c4 10 f c1 10 f c3 4.7 f 0.1 f 0.1 f 1 f 20k 330pf 15k 10.0k 16.5k 30.1k 100k l2 4.7 h l1 3.3 h pgood out2 5v 600ma out3 ?v 300ma out1 3.3v 1.4a d2 10.0k d1 d3a 1nf 2.2nf d3b d5 47k 5v load should be less than 1/2 5v load (see design note 100). c1, c2, c4: taiyo yuden jmk316bj106ml c3: taiyo yuden tmk325bj475ml d1, d2: microsemi ups140 or on semi mbrm140 d3: bat-54a d5: on semi mbr0530 l1: sumida cr43-3r3 l2: coiltronics ctx5-1a typical applicatio s u v in 6v to 16v run/ss1 run/ss2 pg1 pg2 v c1 v c2 fb1 fb2 boost1 sw1 boost2 sw2 lt1940 v in gnd c1 22 f c3 4.7 f 0.1 f 0.1 f 6.8k 16.5k 100k l2 4.1 h l1 4.1 h out2 3.3v 2.4a d2 d3b d1 d3a 10.0k 680pf 330pf 1nf d1, d2: microsemi ups120 d3: bat-54a l1, l2: sumida cdrh5d18-4r1 c1: taiyo yuden jmk316bj226ml c3: taiyo yuden emk325bj475mn pgood 1940 ta06
lt1940/lt1940l 19 1940fa u package descriptio information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. typical applicatio s u 19v regulated input boost2 sw2 fb2 v c2 pg2 run/ss2 boost1 sw1 fb1 v c1 pg1 run/ss1 lt1940 v in gnd 1940 ta08 1nf 4.7 f 0.1 f 0.1 f 20k 1.5nf 10k 10.7k 30.1k 100k l1 15 h l2 4.7 h ?v 3ma 25v 3ma 5v 1.2a d2 d7 10k d1 d3 1nf 1nf d4a d4b d5b d6 22 f 0.022 f 10 f 10 f 1 f + d1, d2: on semi mbrm140t3 d3: central cmpd914 d4, d5: bat-54s 220pf 220pf 1 f 22 22 22 c10 1 f 13v 300ma d5a d6, d7: 6.2v zener l1: sumida cdrh4d28-4r7 l2: sumida cdrh5d28-150 tft lcd supply fe package 16-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663) exposed pad variation ba fe16 (ba) tssop 0203 0.09 ?0.20 (.0036 ?.0079) 0 ?8 0.45 ?0.75 (.018 ?.030) 4.30 ?4.50* (.169 ?.177) 6.40 bsc 134 5 6 7 8 10 9 4.90 ?5.10* (.193 ?.201) 16 1514 13 12 11 1.10 (.0433) max 0.05 ?0.15 (.002 ?.006) 0.65 (.0256) bsc 2.74 (.108) 2.74 (.108) 0.195 ?0.30 (.0077 ?.0118) 2 millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in recommended solder pad layout 3. drawing not to scale 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 2.74 (.108) 2.74 (.108) see note 4 4. recommended minimum pcb metal size for exposed pad attachment
lt1940/lt1940l 20 1940fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com ? linear technology corporation 2001 lt/tp 0204 1k rev a ? printed in usa related parts typical applicatio u part number description comments lt1765 25v, 2.75a (i out ), 1.25mhz, v in : 3v to 25v, v out(min) : 1.20v, i q : 1ma, i sd : 15 m a high efficiency step-down dc/dc converter s8, tssop16e package lt1766 60v, 1.2a (i out ), 200khz, v in : 5.5v to 60v, v out(min) : 1.2v, i q : 2.5ma, i sd : 25 m a high efficiency step-down dc/dc converter tssop16/tssop16e package lt1767 25v, 1.2a (i out ), 1.25mhz, v in : 3v to 25v, v out(min) : 1.2v, i q : 1ma, i sd : 6 m a high efficiency step-down dc/dc converter ms8, ms8e package lt1944 dual output 350ma i sw , constant off-time, v in : 1.2v to 15v, v out(max) : 34v, i q : 20 m a, i sd : <1 m a, high efficiency step-up dc/dc converter ms package lt1944-1 dual output 150ma i sw , constant off-time, v in : 1.2v to 15v, v out(max) : 34v, i q : 20 m a, i sd : <1 m a, high efficiency step-up dc/dc converter ms package lt1945 dual output, pos/neg, 350ma i sw , constant off-time, v in : 1.2v to 15v, v out(max) : 34v, i q : 20 m a, i sd : <1 m a, high efficiency step-up dc/dc converter ms package package lt1956 60v, 1.2a (i out ), 500khz, v in : 5.5v to 60v, v out(min) : 1.2v, i q : 2.5ma, i sd : 25 m a high efficiency step-down dc/dc converter tssop16/tssop16e package ltc3407 dual 600ma, 1.5mhz, synchronous step-down regulator v in : 2.5v to 5.5v, v out(min) : 0.6v, i q : 40 m a, mse package ltc3411 1.25a (i out ), 4mhz, v in : 2.5v to 5.5v, v out(min) : 0.8v, i q : 60 m a, i sd : <1 m a synchronous step-down dc/dc converter ms package ltc3412 2.5a (i out ), 4mhz, v in : 2.5v to 5.5v, v out(min) : 0.8v, i q : 60 m a, i sd : <1 m a synchronous step-down dc/dc converter tssop16e package lt3430 60v, 2.75a (i out ), 200khz, v in : 5.5v to 60v, v out(min) : 1.20v, i q : 2.5ma, i sd : 25 m a high efficiency step-down dc/dc converter tssop16e package ltc3701 two phase,dual, 500khz, constant frequency, v in : 2.5v to 10v, v out(min) : 0.8v, i q : 460 m a, i sd : 9 m a current mode, high efficiency step-down ssop-16 package dc/dc controller low ripple, low profile 5v to 3.3v/2.4a maximum height = 1.4mm v in 4.8v to 7v run/ss1 run/ss2 pg1 pg2 v c1 v c2 fb1 fb2 boost1 sw1 boost2 sw2 lt1940l v in gnd c1 20 f c3 2.2 f 0.1 f 0.1 f 4.7k 16.5k 100k l2 3.3 h l1 3.3 h out2 3.3v 2.4a d2 d4a d1 d3a d4b d3b 10k 1500pf 330pf 1nf 0.47 f d1, d2: microsemi ups120 d3, d4: bat-54s l1, l2: coilcraft lpo1704-332m pgood 1940 ta07 c1: 2x taiyo yuden jmk212bj106ml c3: 2x taiyo yuden emk212bj105mn

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